Synplify pro clock constraint code#
For designers targeting Altera FPGAs, the new version of the Synplify Premier tool provides high reliability capabilities, such as triple modular redundancy (TMR) and automatic inference of error-correcting code (ECC) memories. For engineers targeting Xilinx 7 Series devices, new automated constraints setup assistance and checking for Xilinx's Vivado Design Suite simplifies migration from the Xilinx ISE design software, saving time and enhancing quality of results. The 2012.09 Synplify Premier release also delivers significant enhancements for engineers targeting Altera and Xilinx FPGAs and, for the first time, includes support for Achronix Speedster 22i HD FPGAs. These features enable FPGA designers and engineers deploying FPGA-based prototypes such as Synopsys' HAPS systems to cut weeks off their design project schedules.
The 2012.09 Synplify releases include new multiple error isolation and incremental fix capabilities that accelerate FPGA implementation.
Synplify pro clock constraint verification#
(Nasdaq:SNPS), a global leader accelerating innovation in the design, verification and manufacture of chips and systems, today announced the latest release of the Synopsys Synplify Pro® and Synplify® Premier FPGA synthesis tools. New Features Include Fast Error Identification, Incremental Fix and Customizable Reporting for Faster FPGA Implementation and Prototype Bring-Up
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